Cirrus Logic EP93 Series User Manual page 359

TestCtl
31 30 29 28
15 14 13 12
Address:
0x8001_0008 - Read/Write
Chip Reset:
0x0000_0000
Soft Reset:
0x0000_0000
Definition:
Test Control Register
Bit Descriptions:
RSVD:
MACF:
MFDX:
DB:
IntEn
31 30 29 28
RSVD / RWIE RxMIE RxBIE
15 14 13 12
RSVD RSVD MIIIE
DS785UM1
27 26 25
11 10 9
RSVD
Reserved. Unknown During Read.
MAC Fast. When set, internal MAC timers for link pulses
and collision backoff are scaled in order to speed-up
controller testing. When clear, normal timing is used.
MAC Full Duplex. This bit is used to enable full duplex
operation, when set, the transmitter ignores carrier sense
for transmit deferral. For normal loopback testing this bit
should be set.
Disable backoff. When set, the backoff algorithm is
disabled. The MAC transmitter looks only for completion of
the Inter Frame Gap before starting transmission. When
clear, the backoff algorithm is used as described in
Section 9.1.4 on page
27 26 25
RxSQIE TxLEIE ECIE TxUHIE
11 10 9
PHYSIE TIE RSVD SWIE
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
24 23 22 21
RSVD
8 7 6 5
MACF MFDX DB
9--7.
24 23 22 21
RSVD
8 7 6 5
RSVD
EP93xx User's Guide
20 19 18 17
4 3 2 1
RSVD
20 19 18 17
MOIE TxCOIE
4 3 2 1
TSQIE REOFIE REOBIE
9
16
0
16
RxROIE
0
RHDRIE
9-57