Cirrus Logic EP93 Series User Manual page 384

1/10/100 Mbps Ethernet LAN Controller
EP93xx User's Guide
TXDEnq
9
31 30
15 14
Address:
Chip Reset:
Soft Reset:
Definition:
Bit Descriptions:
TXStsQBAdd
31 30
15 14
Address:
Chip Reset:
9-82
29 28 27 26
13 12 11 10
RSVD
0x8001_00BC - Read/Write
0x0000_0000
Unchanged
Transmit Descriptor Enqueue register. The Transmit Descriptor Enqueue
register is used to define the number of valid descriptors available in the
transmit descriptor queue. Only the Transmit descriptor Increment field is
writable and any value written to this field will be added to the existing
Transmit Descriptor Value. When complete descriptors are read by the MAC,
the Transmit Descriptor Value is decremented by the number read. For
example if the Transmit Descriptor Value is 0x07, and the Host writes 0x03 to
the Transmit Descriptor Increment, the new Value will be 0x0A. If the controller
then reads two descriptors, the Value will be 0x08.
RSVD:
TDV:
TDI:
29 28 27 26
13 12 11 10
0x8001_00C0 - Read/Write
Copyright 2007 Cirrus Logic
25 24 23 22
TDV
9 8 7 6
Reserved. Unknown During Read.
Transmit Descriptor Value.
Transmit Descriptor Increment.
25 24 23 22
TSQBA
9 8 7 6
TSQBA
21 20 19 18
5 4 3 2
TDI
21 20 19 18
5 4 3 2
17 16
1 0
17 16
1 0
DS785UM1