Cirrus Logic EP93 Series User Manual page 680

2
I S Controller
EP93xx User's Guide
Bit Descriptions:
21
I2SRX0En
31 30
15 14
Address:
Default:
efinition:
D
Bit Descriptions:
I2SRX1En
31 30
15 14
Address:
Default:
efinition:
D
21-24
RSVD:
WL:
29 28 27 26
13 12 11 10
0x8082_0064 - Read/Write
0x0000_0000
RX0 Channel Enable
RSVD:
i2s_rx0_EN:
29 28 27 26
13 12 11 10
0x8082_0068 - Read/Write
0x0000_0000
RX1 Channel Enable
Reserved. Unknown During Read. Must be written as "0".
Receive Word Length.
00 - 16 bit mode
01 - 24 bit mode
10 - 32 bit mode
25 24 23 22
RSVD
9 8 7 6
RSVD
Reserved. Unknown During Read. Must be written as "0".
RX0 Channel Enable
25 24 23 22
RSVD
9 8 7 6
RSVD
Copyright 2007 Cirrus Logic
21 20 19 18
5 4 3 2
21 20 19 18
5 4 3 2
17 16
1 0
i2s_rx0_EN
17 16
1 0
i2s_rx1_EN
DS785UM1