Table 10-10. Dma Global Interrupt (Dmaglint) Register - Cirrus Logic EP93 Series User Manual

Address:
0x8000_03C0 - Read/Write
Definition:
DMA Global Interrupt Register. This register indicates which channels have an
active interrupt. It is a read only register.
Bit Descriptions:
RSVD:
D0 - D1:
DMAChArb
31 30 29 28
15 14 13 12
Address:
0x8000_0380 - Read/Write
DS785UM1
Reserved. Unknown During Read.
These interrupts are per channel interrupts, as shown in
Table 10-10. Each bit is a logical OR of the INTERRUPT
register per channel. There are no dedicated storage of
these channel interrupts. Once each Channel's Interrupts'
are clear, the associated channel interrupt is clear.
Note: The order of the internal M2P channel interrupts is
for compatibility reasons with previous versions of
software.

Table 10-10. DMA Global Interrupt (DMAGlInt) Register

Bit No.
D[31:12]
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
27 26 25 24
11 10 9 8
RSVD
Copyright 2007 Cirrus Logic
Description
RSVD
M2M Channel 1 Interrupt
M2M Channel 0 Interrupt
M2P Channel 8 Interrupt
M2P Channel 9 Interrupt
M2P Channel 6 Interrupt
M2P Channel 7 Interrupt
M2P Channel 4 Interrupt
M2P Channel 5 Interrupt
M2P Channel 2 Interrupt
M2P Channel 3 Interrupt
M2P Channel 0 Interrupt
M2P Channel 1 Interrupt
23 22 21
RSVD
7 6 5
DMA Controller
EP93xx User's Guide
20 19 18 17
4 3 2 1
10
16
0
CHARB
10-45