Samsung S5PC100 User Manual page 510

S5PC100 USER'S MANUAL (REV1.0)
1.8.1 ATA_UDMA_TIME Register Setting Example
The "tackenv" minimum time is 20ns in the system clock of 100MHz (10ns). It gives 2; "tackenv" divided by 10ns.
This case has no residual, therefore the udma_tackenv[3:0] assigns 1 which is 2 minus 1. If it has residual, assign
the quotient at udma_tackenv[3:0].
ATA_UDMA_TIME (Tpara) = UDMA mode(min, max) / system clock – 1
tUDMA0(Timing Parameter of UDMA Mode 0)
tackenv: 20/10 = 2
tss: 50/10 = 5
trp: 160/10 = 16
tdvs: 70/10 = 7
tdvh: 50/10 = 5
(tdvh minimum timing is 6.2ns, but the timing parameter sets 50ns since the tDVS and tDVH summation is 120ns)
The Table 5.5-6 shows True-IDE Mode Control Signaling:
nCE2 nCE1 A2
1 0 0
1 1 X
1 0 0
1 0 0
1 0 0
1 0 1
1 0 1
1 0 1
1 0 1
0 1 1
udma_tackenv value = 2 - 1 = 1
udma_tss value = 5 - 1 = 4
udma_trp value = 16 -1 = 15
udma_tdvs value = 7 - 1 =6
udma_tdvh value = 5 - 1 = 4
Table 5.5-6 True-IDE Mode I/O Decoding
A1 A0 nDMACK
0 0 1
X X 0
0 1 1
1 0 1
1 1 1
0 0 1
0 1 1
1 0 1
1 1 1
1 0 1
: 32'h04_06_0f_4_1
udma_tackenv[3 :0]
udma_tss[7:4]
udma_trp[15:8]
udma_tdvs[23:16]
udma_tdvh[27:24] : 0x4
nIORD=0
PIO RD data
DMA RD data
Error Register
Sector Count
Sector No.
Cylinder Low
Cylinder High
Select Card/Head
Status
Alt Status
CF CONTROLLER
nIOWR=0
PIO WR data
DMA WR data
Feature
Sector Count
Sector No.
Cylinder Low
Cylinder High
Select Card/Head
Command
Device Control
: 0x1
: 0x4
: 0x0f
: 0x06
Note
8 or 16 bit
16bit
8 bit
8 bit
8 bit
8 bit
8 bit
8 bit
8 bit
8 bit
5.5-15