Samsung S5PC100 User Manual page 984

S5PC100 USER'S MANUAL (REV1.0)
9.15 TIMEOUT CONTROL REGISTER
Timeout Control Register
•
TIMEOUTCON0, R/W, Address = 0xED80_002E
•
TIMEOUTCON1, R/W, Address = 0xED90_002E
•
TIMEOUTCON2, R/W, Address = 0xEDA0_002E
At the initialization of the Host Controller, the Host Driver sets the Data Timeout Counter Value according to the
Capabilities register.
TIMEOUTCON Bit
Reserved [7:4]
TIMEOUTCON [3:0]
Reserved
Data Timeout Counter Value
This value determines the interval by which DAT line timeouts are
detected. Refer to the Data Timeout Error in the Error Interrupt
Status register for information on factors that dictate timeout
generation. Timeout clock frequency is generated by dividing the
base clock TMCLK value by this value. While setting this register,
prevent inadvertent timeout events by clearing the Data Timeout
Error Status Enable (in the Error Interrupt tatus Enable register)
1111b Reserved
27
1110b TMCLK x 2
26
1101b TMCLK x 2
.............. ...
14
0001b TMCLK x 2
13
0000b TMCLK x 2
Description
SD/MMC CONTROLLER
Reset Value
0
0
8.12-49