Samsung S5PC100 User Manual page 162

CLOCK CONTROLLER
7 DETAILED CLOCK DESCRIPTION
7.1 CPU AND BUS CLOCK
Cortex A8 supports only synchronous mode between CPU and bus (D0 Sync at Figure 2.3-5). D0 and D1 are
asynchronous to each other.
Some clocks can be gated by using SFR.
Clock
HCLKD0, PCLKD0
HCLKD0_SECSS
SCLK_ONENAND, SCLK_ONENAND2
HCLK
PCLK
Caution) ARM clock setting
Clock to ARM (ARMCLK) must be divided when using APLL. It means that at least one of the ARM clock dividers
(DIV and DIV ) must be set to more than 1 (Possible ARM clock division value = 2, 3, ~ 8, 10, 12, 14, 16).
APLL ARM
As shown in Figure 2.3-5, DIV
please consider upper-limit of dividers when setting. If PLL clock is more than 667MHz, you cannot use DOUT
path. Use MOUT path for MUX
MPLL
2.3-12
Figure 2.3-5 CPU and Bus Clock
Table 2.3-6. CPU and Bus Clock
CLK_GATE_D0_0, CLK_GATE_D0_1, CLK_GATE_D0_2
CLK_GATE_D0_0[5]
CLK_GATE_SCLK_0[2]
CLK_GATE_D1_0, CLK_GATE_D1_1, CLK_GATE_D1_2
CLK_GATE_D1_3, CLK_GATE_D1_4, CLK_GATE_D1_5
divides up-to 1.334GHz input, DIV
APLL
.
AM
S5PC100 USER'S MANUAL (REV1.0)
Related SFR
and DIV divides up-to 667MHz input,
ARM APLL2
AM