Samsung S5PC100 User Manual page 863

USB2.0 HS OTG
8.2.3 OTG Reset Control Register (ORSTCON, R/W, address = 0xED30_0008)
ORSTCON Bit
Reserved [31:3]
phylnk_sw_rst [2]
link_sw_rst [1]
phy_sw_rst [0]
8.10 -20
Figure 8.10-4 OTG PHY Clock Path
-
OTG Link Core phy_clock domain S/W Reset
OTG Link Core hclk domain S/W Reset
OTG PHY 2.0 S/W Reset
The phy_sw_rst signal must be asserted for at least 10us
Description
S5PC100 USER'S MANUAL (REV1.0)
R/W Reset Value
R/W
R/W
R/W
29'h0
1'b0
1'b0
1'b1