Samsung S5PC100 User Manual page 633

S5PC100 USER'S MANUAL (REV1.0)
4 UART INPUT CLOCK DIAGRAM DESCRIPTION
Clock Controller
APLL Out
MPLL Out
EPLL Out
XuCLK
S5PC100X provides UART with a variety of clock. As described in the Figure 8.1-, UART is able to select clock
from PCLK, XuCLK which come from PAD or SCLK_UART which is from clock controller. We can also select
SCLK_UART among PLLs. To select SCLK_UART, please refer to the Clock Controller.
4.1 SETTING SEQUENCE OF SPECIAL FUNCTION REGISTER
Special Function Register should be set as the following sequence.
1. Set Line control register(ULCON#) to set a frame format.
2. Set Control register(UCON#) without Transmit mode bits and Receive mode bits.
3. Set 1'b1 on TX FIFO Reset bit and RX FIFO Reset bit of FIFO control register(UFCON) to reset TX FIFO and
RX FIFO.
4. Set FIFO control register(UFCON#) to set Triger Levels and Enable TX FIFO and RX FIFO
5. Set Modem control register(UMCON#).
6. Set Baud rate divisior register(UBRDIV#) and Dividing slot register(UDIVSLOT#) to set BAUD rate.
Choose CPU mode or DMA mode and then follow below sequence.
- In case of CPU mode
8. Set Transmit mode and Receive mode bits to 2'b01 of Control register(UCON#) to enable interrupt mode
9. Put FIFO.
- In case of DMA mode
8. Set Transmit mode and Receive mode bits of Control register(UCON#) to 2'b10 or 2'b11 to enable dma mode.
9. Turn on DMA
UART
SCLK_UART
BCLK
PCLK
Clock_Selection[11:10]
Figure 8.1-8 Input Clock Diagram for UART
UCLK_Generator
UCLK
1/N
UBDIV UDIVSLOT
UART
8.1-9