Samsung S5PC100 User Manual page 677

SPI CONTROLLER
4.2.7 SPI TX Data Register
•
SPI_TX_DATA, W, Address = 0xEC30_0018
•
SPI_TX_DATA, W, Address = 0xEC40_0018
•
SPI_TX_DATA, W, Address = 0xEC50_0018
SPI_TX_DATAn
TX_DATA
4.2.8 SPI RX Data Register
•
SPI_RX_DATA0, R, Address = 0xEC30_001C
•
SPI_RX_DATA1, R, Address = 0xEC40_001C
•
SPI_RX_DATA2, R, Address = 0xEC50_001C
SPI_RX_DATAn
RX_DATA
4.2.9 Packet Count Register
•
PACKET_CNT_REG0, R/W, Address = 0xEC30_0020
•
PACKET_CNT_REG1, R/W, Address = 0xEC40_0020
•
PACKET_CNT_REG2, R/W, Address = 0xEC50_0020
PACKET_CNT_REGn
PACKET_CNT_EN
COUNT_VALUE
8.3-12
Bit
This field contains the data to be transmitted over the SPI
[31:0]
channel.
Bit
This field contains the data to be received over the SPI
[31:0]
channel.
Bit
Enable bit for packet count
[16]
0 = Disable
[15:0] Packet count value
S5PC100 USER'S MANUAL (REV1.0)
Description
Description
Description
1 = Enable
Reset Value
0
Reset Value
0
Reset Value
0
0