Samsung S5PC100 User Manual page 490

S5PC100 USER'S MANUAL (REV1.0)
7.15 MAIN DATA AREA ECC0 STATUS REGISTER (NFMECC1, R, ADDRESS = 0XE720_0038)
•
If ECCType is 1 bit ECC.
NFMECC1 Bit
MECC1_3 [31:24]
MECC1_2 [23:16]
MECC1_1 [15:8]
MECC1_0 [7:0]
NOTE: The NAND flash controller generates NFMECC0/1 if read or write main area data while the
MainECCLock(NFCONT[7]) bit is '0'(Unlock).
•
If ECCType is 4 bit ECC.
NFMECC1 Bit
Reserved [31:24]
th
7 Parity [23:16]
th
6 Parity [15:8]
th
5 Parity [7:0]
NOTE: The NAND flash controller generates these ECC parity codes if write main area data while the MainECCLock
(NFCON[7]) bit is '0'(unlock).
ECC3 data[15:8]
ECC2 data[15:8]
ECC1 data[15:8]
ECC0 data[15:8]
Reserved
th
7 Check Parity generated from main area (512-byte)
th
6 Check Parity generated from main area (512-byte)
th
5 Check Parity generated from main area (512-byte)
Description
Description
NAND FLASH CONTROLLER
Reset Value
0xFF
0xFF
0xFF
0xFF
Reset Value
0x00
0x00
0x00
0x00
5.4-25