Samsung S5PC100 User Manual page 404

S5PC100 USER'S MANUAL (REV1.0)
4.2.3 Memory Chip0 Configuration Register (MemConfig0, R/W, Address=0xE600_0008)
MEMCONFIG0
chip_base [31:24]
chip_mask [23:16]
chip_map [15:12]
chip_col [11:8]
chip_row [7:4]
chip_bank [3:0]
Bit
AXI Base Address
AXI base address [31:24] = chip_base,
For example, if chip_base = 0x20, then AXI base address of
memory chip0 becomes 0x2000_0000.
AXI Base Address Mask
Upper address bit mask to determine AXI offset address of
memory chip0.
0 = Corresponding address bit is not to be used for comparison
1 = Corresponding address bit is to be used for comparison
This bit field is used to check whether 'accessed address' &
'mask address' is equal to 'base address'. For example, if AXI
base address of memory chip0 is 0x2000_0000 and AXI Base
address mask is 0xF8, then memory chip0 has an address
range of 0x2000_0000 ~ 0x27FF_FFFF.
Address Mapping Method (AXI to Memory)
0x0 = Linear ({bank, row, column, width}),
0x1 = Interleaved ({row, bank, column, width}),
0x2 ~ 0xf = Reserved
Number of Column Address Bits
0x0 = 7 bits,
0x1 = 8 bits,
0x2 = 9 bits,
0x3 = 10 bits,
0x4 ~ 0xf = Reserved
Number of Row Address Bits
0x0 = 12 bits,
0x1 = 13 bits,
0x2 = 14 bits,
0x3 = 15 bits,
0x4 ~ 0xf = Reserved
Number of Banks
0x0 = 1 bank,
0x1 = 2 banks,
0x2 = 4 banks,
0x3 = 8 banks,
0x4 ~ 0xf = Reserved
Description
DRAM CONTROLLER
Reset
R/W
Value
R/W 0x20
R/W 0xF8
R/W 0x0
R/W 0x3
R/W 0x1
R/W 0x2
5.1-21