Samsung S5PC100 User Manual page 619

REAL TIME CLOCK
13.2 REAL TIME CLOCK CONTROL REGISTER (RTCCON, R/W, ADDRESS = 0XEA30_0040)
The RTCCON register consists of 9 bits such as the RTCEN, which controls the read/ write enable of the BCD
SEL, CNTSEL, CLKRST, TICCKSEL and TICEN for testing.
RTCEN bit controls all interfaces between the CPU and the RTC, therefore it should be set to 1 in an RTC control
routine to enable data read/ write after a system reset.Before power off, the RTCEN bit should be cleared to 0 to
prevent inadvertent writing into RTC registers.
RTCCON Bit
Reserved [31:9]
TICEN [8]
TICCKSEL [7:4]
CLKRST [3]
CNTSEL [2]
CLKSEL [1]
RTCEN [0]
7.4-8
Reserved
Tick timer enable
0 = Disables
1 = Enables
Tick timer sub clock selection.
4'b0000 = 32768 hz
4'b0010 = 8192 hz
4'b0100 = 2048 hz
4'b0110 =512 hz
4'b1000 =128 hz
4'b1010 =32 hz
4'b1100 =8 hz
4'b1110 =2 hz
RTC clock count reset.
0 = No reset
1 = Reset
BCD count select.
0 = Merge BCD counters
1 = Reserved (Separate BCD counters)
BCD clock select.
15
0 = XTAL 1/2 divided clock
1 = Reserved (XTAL clock only for test)
RTC control enable.
0 = Disables
1 = Enables
Note: If RTCEN is enable, BCD time count setting, RTC clock counter reset
and read operation is performed.
Description
4'b0001 = 16384 hz
4'b0011 = 4096 hz
4'b0101 =1024 hz
4'b0111 =256 hz
4'b1001 =64 hz
4'b1011 =16 hz
4'b1101 =4 hz
4'b1111 =1 hz
S5PC100 USER'S MANUAL (REV1.0)
Reset Value
0
0
4'b0000
0
0
0
0