Samsung S5PC100 User Manual page 177

S5PC100 USER'S MANUAL (REV1.0)
9.2 (OHTERS) REGISTER MAP – CLOCK CONTROLLER
Register
2.1 SW RESET registers
SWRESET
Reserved
ONENAND_SWRESET
Reserved
2.2 CPU registers
GENERAL_CTRL
GENERAL_STATUS
Reserved
2.3 Memory registers
MEM_SYS_CFG
Reserved
2.4 Multimedia registers
CAM_MUX_SEL
MIXER_OUT_SEL
LPMP3_MODE_SEL
Reserved
2.5 Test registers
MIPI_PHY_CON0
Reserved
MIPI_PHY_CON1
Reserved
HDMI_PHY_CON0
Reserved
SFRs consist of three parts. The SFRs, whose address are 0xE010_0XXX, controls clock-related logics. They
control the output frequency of three PLLs, clock source selection, clock divider ratio and clock gating. The SFRs,
whose address is 0xE010_8XXX, control the power management block. The SFRs, whose address is
0xE02_0XX, has some miscellaneous information.
Address R/W
0xE020_0000
0xE020_0000 R/W
0xE020_0004 R/W
0xE020_0008 R/W
0xE020_000C
~ R/W
0xE020_00FC
0xE020_0100
0xE020_0100 R/W
0xE020_0104 R
0xE020_0108 ~
0xE020_01FC
0xE020_0200
0xE020_0200 R/W
0xE020_0204 ~
0xE020_02FC
0xE020_0300
0xE020_0300 R/W
0xE020_0304 R/W
0xE020_0308 R/W
0xE020_030C
~ R/W
0xE020_03FC
0xE020_0400
0xE020_0400 R/W
0xE020_0404 ~
0xE020_0410
0xE020_0414 R/W
0xE020_0418 ~
R/W
0xE020_041C
0xE020_0420
0xE020_0424 ~
0xE02F_FFFC
Description
Generate software reset
Reserved
OneNAND controller setting
Reserved
General Control Register
General Status Register
Reserved
ENDIAN & EBI configuration
Reserved
Camera mapping to FIMC selection
Video Mixer output to TVENC / HDMI
selection
Low power MP3 mode selection
Reserved
MIPI D-PHY control register0
Reserved
MIPI D-PHY control register1
Reserved
HDMI PHY control register0
Reserved
CLOCK CONTROLLER
Reset Value
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
2.3-27