Samsung S5PC100 User Manual page 802

USB HOST CONTROLLER S5PC100 USER'S MANUAL (REV1.0)
3 OPERATION
3.1 OPERATION
3.1.1 Basic Operations
A USB system consists of four main components: two of these, the client software and the host controller driver,
are implemented in software; the other two areas (host controller and the device controller) are implemented in
hardware. The host controller driver and the host controller work together to serially transfer data between a
shared memory data structure and the USB controller. The USB host controller consists of an OHCI compliant
core, a bus interface unit to connect it the system bus, two small FIFOs for buffering data in and out, 2 input pins,
2 output pins, and the transceivers located in the pad unit. The bus interface unit connects to the system bus for
register access and for writing and reading of the FIFOs. The registers must be accessed as 32-bit entities on 32-
bit aligned addresses.
The serial information transmitted and received by the USB host (USBH) contains layers of communications
protocols, the most basic of which are fields. USBH fields include sync, packet identifier, address, Endpoint,
Frame Number, data, and CRC fields. Fields are used to produce packets. Depending on the packet function, a
different combination and number of fields can be used. Packet types include token, start of frame, data, and
handshake. There are four data transfer types define in USB: bulk, control, interrupt, and isochronous. Packets
are assembled into groups to produce frames. Data transfers are grouped into two categories: Periodic
(Isochronous and Interrupt) and Non-periodic (Control and Bulk). Fields inside of the Endpoint Descriptor (ED)
and Transfer Descriptor (TD) memory structures define what type of transfer is to take place.
There are two communication channels between the host controller and the host controller driver. The first
channel uses a set of registers to control, status and list pointers. The second communication channel is the Host
Controller Communication Area (HCCA). The HCCA contains pointers to the interrupt ED, done queue, and status
information associated with start of frame processing. The USB host controller functions as a "smart" DMA
operating on linked lists (EDs and TDs) created by the HCD and located in system memory. The HCD assigns an
Endpoint Descriptor to each Endpoint in the system. The information in these descriptors include: maximum
packet size, the Endpoint address, the speed of the Endpoint, and the direction of data flow. A queue of TDs is
linked to the ED for a specific Endpoint. The TDs contain information on data toggle, shared memory buffer
location and completion status codes. The HCD creates these ED lists and TD queues then passes control to the
UHC for processing (by setting bits two through five of the UHCCON register). The HCD adds to the TD queues
and the UHC removes from the queues by linking a finished TD with the Done Queue. The UHC updates fields
(such as Current Buffer Pointer and Condition Code) in the TD in system memory space upon completion of a TD.
Head pointers to the Bulk and Control ED lists are maintained in the UHC (UHCBHDED and UHCHDED
registers). The HCD must initialize these registers. Figure 8.9-1 illustrates a typical list structure.
8.9-2