Samsung S5PC100 User Manual page 951

SD/MMC CONTROLLER S5PC100 USER'S MANUAL (REV1.0)
(7) Wait for the Command Complete Interrupt.
(8) Write 1 to the Command Complete (STACMDCMPLT) in the Normal Interrupt Status register to clear this bit.
(9) Read Response register and get necessary information in accordance with the issued command.
(10) Wait for the Transfer Complete Interrupt and DMA Interrupt.
(11) If Transfer Complete (STATRANCMPLT) is set 1, go to Step (14) else if DMA Interrupt is set to 1; proceed to
Step (12). Transfer Complete is higher priority than DMA Interrupt.
(12) Write 1 to the DMA Interrupt in the Normal Interrupt Status register to clear this bit.
(13) Set the next system address of the next data position to the System Address register and go to Step (10).
(14) Write 1 to the Transfer Complete and DMA Interrupt in the Normal Interrupt Status register to clear this bit.
NOTE: Step (2) and Step (3) can be executed simultaneously. Step (5) and Step (6) can also be executed simultaneously.
5 ABORT TRANSACTION
Abort transaction is performed by issuing CMD12 (Stop Command) for a SD memory card and by issuing CMD52
for a SDIO card. There are two cases where the Host Driver needs to do an Abort Transaction. The first case is if
the Host Driver stops Infinite Block Transfers. The second case is if the Host Driver stops transfers while a
Multiple Block Transfer is executing.
There are two ways to issue an Abort Command. The first is an asynchronous abort. The second is a
synchronous abort. In an asynchronous abort sequence, the Host Driver issues an Abort Command at anytime
unless Command Inhibit (CMD) in the Present State register is set to 1. In a synchronous abort, the Host Driver
issues an Abort Command after the data transfer stopped by using Stop At Block Gap Request in the Block Gap
Control register.
6 DMA TRANSACTION
DMA allows a peripheral to read and write memory without intervention from the CPU. DMA executes one SD
command transaction. Host Controllers that support DMA supports both single block and multiple block transfers.
The System Address register points to the first data address, and data is then accessed sequentially from that
address. Host Controller registers remains accessible for issuing non-DAT line commands during a DMA transfer.
The result of a DMA transfer is same regardless of the system bus transaction method used. DMA does not
support infinite transfers.
DMA transfers are stopped and restarted using control bits in the Block Gap Control register. If the Stop At Block
Gap Request is set, DMA transfers is suspended. If the Continue Request is set or a Resume Command is
issued, DMA continues to execute transfers. Refer to the Block Gap Control register for details. If SD Bus errors
occur, SD Bus transfers and DMA transfers are stopped. Setting the Software Reset for DAT Line in the Software
Reset register aborts DMA transfers.
8.12-16