Samsung S5PC100 User Manual page 163

S5PC100 USER'S MANUAL (REV1.0) CLOCK CONTROLLER
7.2 LOW POWER MUSIC-PLAY CLOCK
If music is played at D2 clock domain, Audio_CMU module in D2_SS supplies clock for AHB and 5.1ch I2S.
Clock sources of Audio_CMU are EPLL output clock, clock from PAD, and SCLK_AUDIO0 (Refer to "Section
7.10"). Clock source of I2S is dependent to I2S mode. If S5PC100 is operated as I2S master mode, EPLL
supplies I2S clock. If S5PC100 is operated as I2S slave mode, external I2S master supplies I2S clock. Bus clocks,
HCLKD2 and PCLKD2, are asynchronous to I2S clock. So you can freely select clock source for bus.
When LP (Low-Power) Audio mode with 'top off' is used, SCLK_AUDIO0 must not be selected for I2SCLKD2.
SCLK_AUDIO0 is turned off at 'top off' mode.
Figure 2.3-6 Audio_CMU in D2_SS
2.3-13