Samsung S5PC100 User Manual page 238

S5PC100 USER'S MANUAL (REV1.0)
8.2 DEEP-IDLE MODE WAKEUP
Wakeup timing in DEEP-IDLE mode (Top domain on) is shown in Figure 2.4-10, and wakeup timing in DEEP-
IDLE mode (Top domain off) is shown in Figure 2.4-11.
Note that in Figure 2.4-10, ARMCLK is the same as those before DEEP-IDLE mode, but in Figure 2.4-11
ARMCLK is the same as XXTI after wakeup and APLL should be enabled to supply high-frequency for ARM CPU.
ARM_ARESETn is released within XXTI 1424 cycles after wakeup source is asserted.
XXTI
DEEP _ IDLE _ MODE
( internal )
XEINT [ 0 ]
( wakup event )
ARMCLK _ OFF
( internal )
ARMCLK
( internal )
APLL clock out
ARM _ ARESETn
( internal )
APLL / MPLL /
HPLL / EPLL
( internal )
Figure 2.4-10 DEEP-IDLE Mode (Top Domain on) Wakeup Timing
. . .
XXTI 6 cycles
XXTI
Power Management
. . .
ARMCLK is the same as those
before DEEP - IDLE mode .
1424 cycles
2.4-39