Samsung S5PC100 User Manual page 429

S5PC100 USER'S MANUAL (REV1.0)
2 FUNCTIONAL DESCRIPTION
SMC Controller support SMC interface for Bank0 to Bank5.
2.1 NWAIT PIN OPERATION
If the WAIT corresponding to each memory bank is enabled, the nOE duration should be prolonged by the
external nWAIT pin while the memory bank is active. nWAIT is checked from tacc-1. nOE will be deasserted at
the next clock after sampling nWAIT is high. The nWE signal have the same relation with nOE.
HCLK
ADDR
nGCS
nOE
nWAIT
DATA(R)
Tacs
Tcos
Figure 5.2-2 SMC Controller nWAIT Timing Diagram
STATIC MEMORY CONTROLLER
tRC
Tacc=4 Delayed
Sampling nWAIT
5.2-3