Samsung S5PC100 User Manual page 580

S5PC100 USER'S MANUAL (REV1.0)
PCLK
8BIT
PRESCALER
0
PWM_TCLK
8BIT
PRESCALER
1
The Figure 7.1-2 shows the clock generation scheme for individual PWM Channels.
Each timers can generate level interrupts.
TCMPB0
PWM_TCLK
6:1
1/1
MUX
1/2
1/4
1/8
TCMPB1
1/16
6:1
MUX
PWM_TCLK
TCMPB2
PWM_TCLK
6:1
MUX
TCMPB3
PWM_TCLK
1/1
1/2
6:1
MUX
1/4
1/8
1/16
PWM_CLK
6:1
MUX
Figure 7.1-2 PWM TIMER Clock Tree Diagram
TCNTB0
Control
Logic0
TCNTB1
Control
Logic1
TCNTB2
Control
Logic2
TCNTB3
Control
Logic3
TCNTB4
Control
Logic4
PULSE WIDTH MODULATION TIMER
XpwmTOUT0
DeadZone
Generator
Deadzone
XpwmTOUT1
Deadzone
XpwmTOUT2
No pin
No pin
7.1-3