Product Overview; Architectural Overview - Samsung S5PC100 User Manual

S5PC100 USER'S MANUAL (REV1.0)

PRODUCT OVERVIEW

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PRODUCT OVERVIEW

1 ARCHITECTURAL OVERVIEW

S5PC100 is a 32-bit RISC cost-effective, low power, high performance microprocessor solution for mobile phones
and general applications, and integrates an ARM CortexTM-A8 which implements the ARM architecture V7-A with
supporting numerous peripherals.
To provide optimized Hardware (H/W) performance for the 3G and 3.5G communication services, S5PC100
adopts 64-bit internal bus architecture and includes many powerful hardware accelerators for tasks such as
motion video processing, display control and scaling. Integrated Multi Format Codec (MFC) supports encoding
and decoding of MPEG-1/2/4, H.263, H.264 and decoding of VC1, Divx. This Hardware accelerators support real-
time video conferencing and Analog TV out, HDMI for NTSC and PAL mode
The S5PC100 has an optimized interface to external memory capable of sustaining the demanding memory
bandwidths required in high-end communication services. The memory system has Flash/ ROM external memory
ports for parallel access and DRAM port for high bandwidth. DRAM port can be configured to support mobile
DDR, DDR2 or LPDDR2.
Flash/ROM Port supports NAND Flash, NOR-Flash, OneNAND and ROM type external memory.
To reduce total system cost and enhance overall functionality, S5PC100 includes many hardware peripherals
such as TFT 24-bit true color LCD controller, Camera Interface, MIPI DSI, CSI-2 and HSI, System Manager for
power management, CF+, ATA I/F, 4-channel UART, 24-channel DMA, 4-channel Timers, General I/O Ports, 3-ch
IIS, 1-ch S/PDIF, 2-ch CAN bus, IIC-BUS interface, 3-ch HS-SPI, USB Host v1.1, USB OTG v2.0 operating at
high speed (480Mbps), SD Host & High Speed Multi-Media Card Interface and PLLs for clock generation.
Package on Package (POP) option with MCP is available for small form factor applications.
Salient features of S5PC100 are summarized below:
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