Samsung S5PC100 User Manual page 544

S5PC100 USER'S MANUAL (REV1.0)
5.6
1 OVERVIEW
S5PC100 External Bus Interface (EBI), as a peripheral, relies on the memory controllers to release their external
requests for the external bus when they are idle. Because it has no knowledge of when a transfer starts or
completes. It enables for one SROM controller, one OneNAND controller, one NAND Flash controller and one CF
controller to share one external memory bus named as memory port 0.
2 FEATURES
S5PC100 EBI features include:
Memory Port 0 is shared using EBI.
* Reference: ARM PrimeCell External Bus Interface (PL220), ARM DDI 0249B.
•
AMBA AXI 3.0 low power interface (CSYSREQ, CACTIVE, CSYSACK) to prevent memory controller from
accessing memories.
•
Share of pad interface used by 4 memory controllers (SROMC, OneNANDC, NFCON, CFCON).
•
Pad interface ownership is determined by the priority which can be changed.
•
The handshaking between the EBI and the memory controller consists of a three-wire interface, EBIREQ,
EBIGNT, and EBIBACKOFF, all active High.
EBIREQ signals are asserted by memory controllers to indicate that they require external bus access.
The respective arbitrated EBIGNT is issued to the highest priority memory controller.
EBIBACKOFF is output of the EBI to signal that the memory controller must complete the current transfer and
release the bus.
•
The EBI arbitration scheme keeps track of the memory controller that is currently granted and waits for the
transaction from that memory controller to finish (EBIREQ taken Low by the memory controller) before it
grants the next memory controller. If a higher priority memory controller requests the bus then EBIBACKOFF
signal tells the currently granted memory controller to terminate the current transfer as soon as possible.
•
Memory Subsystem gets booting method and CS selection information from the System Controller.
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nCS0 and nCS1 in memory port 0 are dedicated for SROMC.
•
If NAND Flash or OneNAND is selected for boot device, nCS2 is used to access that boot media.
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EBIGNT is required to be deasserted one cycle after EBIREQ is deasserted in sync. mode
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EBIBACKOFF is required to be deasserted one cycle after EBIREQ is deasserted in sync. mode
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In case EBIREQ is deasserted because of higher priority EBIBACKOFF, EBIREQ signal must be low for at
least one clock cycle in sync. mode
•
EBI_REQ duration is not required at least 4 cycle from CSYSREQ to CACTIVE
EXTERNAL BUS INTERFACE
EXTERNAL BUS INTERFACE
5.6-1