Samsung S5PC100 User Manual page 899

USB2.0 HS OTG
DEVICE MODE REGISTERS
These registers are visible only in Device mode and must not be accessed in Host mode, as the results are
unknown. Some of them affect all the endpoints uniformly, while others affect only a specific endpoint. Device
Mode registers fall into two categories:
•
Device Global registers
•
Device logical endpoint-specific registers
8.2.33 Device Configuration Register (DCFG, R/W, Address = 0xED20_0800)
This register configures the core after power-on or after certain control commands or enumeration. Do not make
changes to this register after initial programming.
DCFG Bit
Reserved [31:23] -
EPMisCnt [22:18] IN Endpoint Mismatch Count
Reserved [17:13] -
PerFrInt [12:11] Periodic Frame Interval
DevAddr [10:4]
Reserved [3]
NZSts [2]
OUTHShk
8.10 -56
The application programs this field with a count that determines
when the core generates an Endpoint Mismatch interrupt. The core
loads this value into an internal counter and decrements it. The
counter is reloaded whenever there is a match or if the counter
expires. The width of this counter depends on the depth of the
Token Queue.
Indicates the time within a (micro) frame at which the application
must be notified using the End Of Periodic Frame Interrupt. This can
be used to determine if all the isochronous traffic for that (micro)
frame is complete.
• 2'b00 : 80% of the (micro) frame interval
• 2'b01 : 85%
• 2'b10 : 90%
• 2'b11 : 95%
Device Address
The application must program this field after every SetAddress
control command.
-
Non-Zero-Length Status OUT Handshake
The application uses this field to select the handshake the core
sends on receiving a nonzero-length data packet during the OUT
transaction of a control transfer's Status stage.
• 1'b0: Sends a STALL handshake on a nonzero-length status OUT
transaction and do not send the received OUT packet to the
application.
• 1'b1: Sends the received OUT packet to the application and send
a handshake based on the NAK and STALL bits for the endpoint in
the Device Endpoint Control register.
Description
S5PC100 USER'S MANUAL (REV1.0)
R/W
R/W
R/W
R/W
R/W
Reset
Value
9'h0
5'h8
5'h0
2'h0
7'h0
1'b0
1'b0