Samsung S5PC100 User Manual page 234

S5PC100 USER'S MANUAL (REV1.0)
7.4 WATCHDOG RESET
Watchdog reset is asserted if software fails to prevent the watchdog timer from timing out. In watchdog reset all
units in S5PC100 (except some registers listed in Table 2.4-15) are reset to their predefined reset states. The
behavior after Watchdog reset is asserted, is the same as Hardware reset case (Refer to "Section 7.1
HARDWARE RESET").
During the watchdog reset, the following actions occur:
• All units (except some registers listed in Table 2.4-15) go into their pre-defined reset state.
• All pins get their reset state, and XnBATF pin is ignored.
• The XnRSTOUT pin is asserted during watchdog reset.
Watchdog reset is activated in NORMAL / IDLE / DEEP-IDLE (Top domain on) mode because watchdog timer
expires with clock.
Watchdog reset is asserted when watchdog timer and reset are enabled (WTCON[5] = 1, WTCON[0]=1) and
watchdog timer is expired.
Watchdog reset is asserted then, the following sequence occurs. :
1. Watchdog Timer (WDT) generates time-out signal.
2. PMU invokes reset signals and initializes internal IPs, and XnRSTOUT are asserted and reset counter is
activated.
3. Reset counter is expired then; internal reset signals and XnRSTOUT are released.
Timing diagram for watchdog reset is shown in Figure 2.4-8.
WDTRST _ REQ
(internal)
GRESETn
(internal)
ARM _ ARESETn
(internal )
XnRSTOUT
Watchdog Timer Module requests watchdog reset
XXTI 1cycle
Figure 2.4-8 Watchdog Reset Timing Diagram
XXTI 279 cycles
XXTI 139 cycles
Power Management
.
2.4-35