Samsung S5PC100 User Manual page 454

S5PC100 USER'S MANUAL (REV1.0)
4.5 INTERRUPT ERROR MASK REGISTER (INT_ERR_MASK, R/W, ADDRESS = 0XE710_0040)
INT_ERR_MASK
Reserved
Cache_Op_Err
Rst_Cmp
Reserved
INT_act
Unsup_Cmd
Locked_Blk
Blk_RW_Cmp
Ers_Cmp
Pgm_Cmp
Load_Cmp
Ers_Fail
Pgm_Fail
Int_TO
Ld_Fail_Ecc_Err
4.6 INTERRUPT ERROR ACKNOWLEDGE REGISTER (INT_ERR_ACK, R/W ADDRESS = 0XE710_0050)
INT_ERR_ACK
Reserved
Cache_Op_Err
Rst_Cmp
Reserved
INT_act
Unsup_Cmd
Locked_Blk
Blk_RW_Cmp
Ers_Cmp
Pgm_Cmp
Load_Cmp
Ers_Fail
Pgm_Fail
Int_TO
Ld_Fail_Ecc_Err
Bit
[31:14] Reserved
[13]
[12]
[11]
[10]
[9]
Mask bits that correspond to the bits in the int_error_status
[8]
register. Setting this bit allows the controller to issue this type
[7] of interrupt. Set through software.
Note: Interrupts are only sent to the host if an interrupt is set
[6]
in the int_error_status register, the corresponding bit is set in
[5]
this register, and the INT_PIN_ENABLE register is set.
[4]
[3]
[2]
[1]
[0]
Bit
[31:14] Reserved
[13]
[12]
[11]
[10]
[9]
[8]
Acknowledge bits that correspond to the bits in the
[7]
int_error_status register. Setting this bit resets or
[6]
acknowledges the associated interrupt. Set by software.
[5]
[4]
[3]
[2]
[1]
[0]
Description
Description
ONENAND CONTROLLER
Reset Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5.3-17