Samsung S5PC100 User Manual page 784

MIPI DSIM
3.2.13 Interrupt mask register (DSIM_INTMSK, R/W, Address = 0xECB0_0x30)
This register masks interrupt sources.
DSIM_INTMSK
MskPllStable
MskSwRstRelease
MskSFRFifoEmpty
MskSyncOverride
Reserved
MskBusTurnOver
MskFrameDone
Reserved
MskLpdrTout
MskTaTout
Reserved
MskRxDatDone
MskRxTE
MskRxAck
MskRxECC
MskRxCRC
Reserved
MskEsc2
MskEsc1
MskEsc0
Reserved
MskSync2
MskSync1
MskSync0
8.7-28
Bit
[31] Indicates that D-phy PLL is stable
[30] Software reset is released
[29] SFR payload FIFO empty
[28] Indicates that a Sync timing has been overridden by
other DSI command transfer.
[27:26] Reserved
[25] Indicates when Bus grant turns over from DSI slave to
DSI master.
[24] Indicates when MIPI DSIM transfers whole image
frame
[23:22] Reserved
[21] LP Rx timeout. See the time out register (0x10)
[20] Turn around Acknowledge Timeout. See the time out
register (0x10)
[19] Reserved
[18] Data receiving complete
[17] TE Rx trigger received
[16] ACK Rx trigger received
[15] ECC multi bit error in LPDR
[14] CRC error in LPDR
[13] Reserved
[12] Escape mode entry error lane2
(For more information refer to standard d-phy
specification)
[11] Escape mode entry error lane1
(For more information refer to standard d-phy
specification)
[10] Escape mode entry error lane0
(For more information refer to standard d-phy
specification)
[9] Reserved
[8] LPDT Sync Error lane2
(For more information refer to standard d-phy
specification)
[7] LPDT Sync Error lane1
(For more information refer to standard d-phy
specification)
[6] LPDT Sync Error lane0
Description
S5PC100 USER'S MANUAL (REV1.0)
R/W Reset Value
-
R/W
R/W
R/W
-
R/W
R/W
-
R/W
R/W
-
R/W
R/W
R/W
R/W
R/W
-
R/W
R/W
R/W
-
R/W
R/W
R/W
-
0
1
1
-
1
1
-
1
1
-
1
1
1
1
1
-
1
1
1
-
1
1
1