Samsung S5PC100 User Manual page 425

DRAM CONTROLLER
Transaction
R/W
Master
ARM R/W
MDMA R/W
G2D R/W
CFCON R/W
CSSYS R/W
FIMC0 R/W
FIMC1 R/W
FIMC2 R/W
JPEG R/W
Rotator R/W
R
FIMD0
R
R
FIMD1
R
R
5.1-42
Table 5.1-1 Master Transaction ID in S5PC100 (1/2)
Transaction ID
12'b0000_0000_0000
12'b0000_0000_0100
12'b0000_0000_1000
12'b0000_0000_1100
12'b0000_0001_0000
12'b0000_0001_0100
12'b0000_0001_1000
12'b0000_0001_1100
12'b0000_0010_0000
12'b0000_0010_0100
12'b0000_0010_1000
12'b0000_0010_1100
12'b0000_0011_0000
12'b0000_0011_0100
12'b0000_0011_1000
12'b0000_0011_1100
12'b0000_0000_0001
12'b0000_0001_0001
12'b0000_0010_0001
12'b0000_0011_0001
12'b0000_0100_0001
12'b0000_0101_0001
12'b0000_0110_0001
12'b0000_0111_0001
12'b0000_1000_0001
12'b0000_0000_0101
12'b0000_0000_1001
12'b0000_0000_1101
12'b0000_0000_0010
12'b0000_0010_0010
12'b0000_0100_0010
12'b0000_0110_0010
12'b0000_1000_0010
12'b0000_1010_0010
12'b0001_1010_0010
12'b0000_1100_0010
12'b0001_1100_0010
12'b0010_1100_0010
Integer data & NEON - Noncacheable or strongly ordered read/write
Integer data & NEON - Shared device read/ write
Integer data & NEON - Cacheable non-burst write
Integer data & NEON - Nonshared device read/ write
Instruction fetch - Noncacheable or strongly ordered
Instruction fetch - Shared or nonshared device
Table walk
Reserved
Cacheable linefill - All except linefill into data cache including PLE
Eviction including PLE
Reserved
Reserved
Cacheable linefill - Linefill into data cache
Cacheable linefill - Linefill into instruction cache
(L2 Noncacheable)
DMA channel0 thread
DMA channel1 thread
DMA channel2 thread
DMA channel3 thread
DMA channel4 thread
DMA channel5 thread
DMA channel6 thread
DMA channel7 thread
DMA manager thread
G2D
CFCON
Coresight AHB access port
Camera IF 0
Camera IF 1
Camera IF 2
JPEG
Rotator
window 0
window 4
window 1
window 2
window 3
S5PC100 USER'S MANUAL (REV1.0)
Description