Samsung S5PC100 User Manual page 594

S5PC100 USER'S MANUAL (REV1.0)
If Manual update bit is 1'b1 and Start/Stop bit is 1'b1, timer counter is not update by new value.
Timer counter value is last value.
5.4 TIMER0 COUNTER REGISTER (TCNTB0, R/W, ADDRESS = 0XEA00_000C)
TCNTB0
Timer 0 Count Buffer
5.5 TIMER0 COMPARE REGISTER (TCMPB0, R/W, ADDRESS = 0XEA00_0010)
TCMPB0
Timer 0 Compare Buffer
5.6 TIMER0 OBSERVATION REGISTER (TCNTO0, R, ADDRESS = 0XEA00_0014)
TCNTO0
Timer 0 Count Observation
NOTE: Counter observation time is dependent on PWM timer clock and PCLK.
When you observe counter value after PWM timer start, wait for delay time( Timer Clock period/2 + 2*PCLK period).
Example) if Prescaler is 4 and Divider mux is 1/2,
Timer clock period = (4+1)*2*PCLK
TCNTO observation delay time = (4+1)*2/2*PCLK+2*PCLK
5.7 TIMER1 COUNTER REGISTER (TCNTB1, R/W, ADDRESS = 0XEA00_0018)
TCNTB1
Timer 1 Count Buffer
5.8 TIMER1 COMPARE REGISTER (TCMPB1, R/W, ADDRESS = 0XEA00_001C)
TCMPB1
Timer 1 Compare Buffer
Bit
[31:0] Timer 0 Count Buffer Register
Bit
[31:0] Timer 0 Compare Buffer Register
Bit
[31:0] Timer 0 Count Observation Register
Bit
[31:0] Timer 1 Count Buffer Register
Bit
[31:0] Timer 1 Compare Buffer Register
PULSE WIDTH MODULATION TIMER
Description
Description
Description
Description
Description
Reset Value
0x0000_0000
Reset Value
0x0000_0000
Reset Value
0x0000_0000
Reset Value
0x0000_0000
Reset Value
0x0000_0000
7.1-17