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DRAM CONTROLLER
3 I/O DISCRIPTION
Function Signal
DDR2SEL
DDR_CSn[1:0]
DDR_SCLK
nSCLK
DDR_
RASn
DDR_
CASn
DDR_
WEn
DDR_
A[31:0]
DDR_
D[31:0]
DDR_
DQM[3:0]
DDR_
DQS[3:0]
DDR_
DQSn[3:0]
DDR_
DDR_CKE[1:0]
5.1-14
I/O
I
Memory Type Selection
O
Memory Chip Select
O
Memory Clock
O
Memory Negative Clock
O
Row Address Selection
O
Column Address Selection
O
Write Enable
I/O
Memory Address Bus
I/O
Memory Data Bus
O
Write Masking Per Byte
I/O
Data Strobe Signal Per Byte
I/O
Data Strobe Negative Signal Per Byte
O
Memory Address, Bank Address, CS, CKE signals
Description
(0; LPDDR1, 1: DDR2, LPDDR2)
S5PC100 USER'S MANUAL (REV1.0)
PAD
XDDR2SEL
Xm1CSn[1:0]
Xm1SCLK
Xm1nSCLK
Xm1RASn
Xm1CASn
Xm1WEn
Xm1ADDR[31:0]
Xm1DATA[31:0]
Xm1DQM[3:0]
Xm1DQS[3:0]
Xm1DQSn[3:0]
* refer to 3.1 table
Type
dedicated
dedicated
dedicated
dedicated
dedicated
dedicated
dedicated
dedicated
dedicated
dedicated
dedicated
dedicated
dedicated
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