Samsung S5PC100 User Manual page 966

S5PC100 USER'S MANUAL (REV1.0)
TRNMOD Bit
RD1WT0 [4]
Reserved [3]
ENACMD12 [2]
ENBLKCNT [1]
ENDMA [0]
Table below shows the summary of how register settings determine types of data transfer.
Determination of Transfer Type
Multi/Single Block Select
0
1
1
1
NOTE: For CE-ATA access, (Auto) CMD12 must be issued after Command Completion Signal Disable.
Data Transfer Direction Select
This bit defines the direction of DAT line data transfers.
The bit is set to 1 by the Host Driver to transfer data from the SD card to
the SD Host Controller and it is set to 0 for all other commands.
1 = Read (Card to Host)
0 = Write (Host to Card)
Reserved
Auto CMD12 Enable
Multiple block transfers for memory require CMD12 to stop the
transaction.
If this bit is set to 1 and last block transfer is complete, the Host
Controller issues CMD12 automatically. The Host Driver does not set
this bit to issue commands that do not require CMD12 to stop data
transfer.
1 = Enable
0 = Disable
Block Count Enable
This bit is used to enable the Block Count register, which is only relevant
for multiple block transfers. If this bit is 0, the Block Count register is
disabled, which is useful in executing an infinite transfer. (Refer to the
Table below "Determination of Transfer Type")
1 = Enable
0 = Disable
DMA Enable
This bit enables DMA functionality. DMA is enabled if it is supported as
indicated in the DMA Support in the Capabilities register. If DMA is not
supported, this bit is meaningless and always read 0. If this bit is set to
1, a DMA operation begins if the Host Driver writes to the upper byte of
Command register (00Fh).
1 = Enable
0 = Disable
Block Count Enable
Don't care
0
1
1
Description
Block Count
Don't care
Don't care
Not Zero
Zero
SD/MMC CONTROLLER
Reset Value
0
0
0
0
0
Function
Single Transfer
Infinite Transfer
Multiple Transfer
Stop Multiple Transfer
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