Samsung S5PC100 User Manual page 933

S5PC100 USER'S MANUAL (REV1.0)
8.3 MODEM INTERFACE CONTROL REGISTER (MIFCON, R/W, ADDRESS = 0XED50_8008)
MIFCON
Reserved
Fixed
DMARXREQEN_1
DMARXREQEN_0
DMATXREQEN_1
DMATXREQEN_0
Reserved
INT2MSMEN
INT2APEN
Reserved
Fixed
8.4 MODEM INTERFACE PORT CONTROL REGISTER (MIFPCON, R/W, ADDRESS = 0XED50_800C)
MIFCON
Reserved [31:7]
ADM_MODE
ADM_WAKE_EN
INT2M_LEVEL
Fixed
Bit
[31:21] Reserved
[20] Shoud write as 1
[19] Enables MSM Write DMA Request (RX 1) to AP (DMA Controller)
[18] Enables MSM Write DMA Request (RX 0) to AP (DMA Controller)
[17] Enables MSM Read DMA Request (TX 1) to AP (DMA Controller)
[16] Enables MSM Read DMA Request (TX 0) to AP (DMA Controller)
[15:4] Reserved
[3] Enables Interrupt to MSM (Modem)
: MSM_nIRQ is interrupt signal enable.
'0' = Disable, '1' = Enable
[2] Enables MSM (Modem) write interrupt to AP
'0' = Disable, '1' = Enable
[1] Reserved
[0] Fixed to 0
Bit
Reserved
[6] Address Muxed mode selection
'0' = Disable, '1' = Enable
Note) XmsmADDR[4] is mapped to XmsmADVn
[5] Address Muxed mode Wakeup Enable
'0' = Disable, '1' = Enable
[4] Interrupt to MSM(Modem) Active High
MSM_nIRQ interrupt signal make active high if this bit is set to
High.
'0' = Disable, '1' = Enable
[3:0] Fixed to 0
Description
Description
MODEM INTERFACE
Reset Value
0
0
0
0
0
0
0
1
0
0
0
Reset Value
0
0
0
0
0
8.11-11