Samsung S5PC100 User Manual page 952

S5PC100 USER'S MANUAL (REV1.0) SD/MMC CONTROLLER
7 ADMA(ADVANCED DMA)
In the SD Host Controller Standard Specification Version 2.00, new DMA transfer algorithm called ADMA
(Advanced DMA) is defined. The DMA algorithm defined in the SD Host Controller Standard Specification Version
1.00 is called SDMA (Single Operation DMA). SDMA had disadvantage that DMA Interrupt generated at every
page boundary disturbs CPU to reprogram the new system address. This SDMA algorithm forms a performance
bottleneck by interruption at every page boundary. ADMA adopts scatter gather DMA algorithm so that higher
data transfer speed is available. The Host Driver can program a list of data transfers between system memory
and SD card to the Descriptor Table before executing ADMA. It enables ADMA to operate without interrupting the
Host Driver. Furthermore, ADMA can support not only 32-bit system memory addressing but also 64-bit system
memory addressing. The 32-bit system memory addressing uses lower 32-bit field of 64-bit address registers.
Support of SDMA and ADMA are optional for the Host Controller. ADMA improves the restriction so that data of
any location and any size can be transferred in system memory. The format of Descriptor Table is different
between them. The Host Controller Specification Ver2.00 defines ADMA as standard ADMA.
7.1 BLOCK DIAGRAM OF ADMA
Figure 8.12- 13 Block Diagram of ADMA
Figure 8.12-13 shows block diagram of ADMA. The Descriptor Table is created in system memory by the Host
Driver. 32-bit Address Descriptor Table is used for the system with 32-bit addressing and 64-bit Address
Descriptor Table is used for the system with 64-bit addressing. Each descriptor line (one executable unit) consists
with address, length and attribute field. The attribute specifies operation of the descriptor line. ADMA includes
SDMA, State Machine and Registers circuits. ADMA does not use 32-bit SDMA System Address Register (offset
0) but uses the 64-bit Advanced DMA System Address register (offset 058h) for descriptor pointer. Writing
Command register triggers off ADMA transfer. ADMA fetches one descriptor line and execute it. This procedure is
repeated until end of descriptor is found (End=1 in attribute).
8.12-17