Samsung S5PC100 User Manual page 797

S5PC100 USER'S MANUAL (REV1.0)
7.2 D-PHY CONTROL REGISTER (CSIS_DPHYCTRL, R/W, ADDRESS = 0XECC0_0004)
This register is used to control of D-phy.
CSIS_DPHYCTRL
Reserved
DPHYOn
7.3 CONFIGURATION REGISTER (CSIS_CONFIG, R/W, ADDRESS = 0XECC0_0008)
CSIS_CONFIG
Reserved
NumOfDatLane
7.4 DPHY STATE REGISTER (CSIS_DPHYSTS, R, ADDRESS = 0XECC0_000C)
CSIS_DPHYSTS
Reserved
StopStateDat
Reserved
StopStateClk
Bit
[31:1] Should not change the value
[0] Enables D-PHY Clock and Data lane
0 = Disable
1 = Enable
Bit
[31:2] Reserved
[1:0] Number of data lane
00 = 1 Data Lane
01 = 2 Data Lane
10 ~ 11 : Reserved
Bit
[31:6] Reserved
[5:4] Data lane [1:0] is in Stop State
[5] : Data Lane 1
[4] : Data Lane 0
[3:1] Reserved
[0] Clock lane is in Stop State
Description
Description
Description
MIPI CSIS
Reset Value
0
0
Reset Value
0
0
Reset Value
0
3
0
1
8.8-7