Samsung S5PC100 User Manual page 874

S5PC100 USER'S MANUAL (REV1.0)
GINTSTS Bit
FetSusp [22]
incompIP [21]
incompl
SOOUT
Incompl [20]
SOIN
OEPInt [19]
Data Fetch Suspended. This interrupt is valid only in DMA mode.
This interrupt indicates that the core has stopped fetching data for
IN endpoints due to the unavailability of TxFIFO space or Request
Queue space. This interrupt is used by the application for an
endpoint mismatch algorithm.
For example, after detecting an endpoint mismatch, the
application:
• Sets a global non-periodic IN NAK handshake
• Disables In endpoints
• Flushes the FIFO
• Determines the token sequence from the IN Token Sequence
Learning Queue
• Re-enables the endpoints
• Clears the global non-periodic IN NAK handshake
If the global non-periodic IN NAK is cleared, the core has not yet
fetched data for the IN endpoint, and the IN token received: the
core generates an "IN token received when FIFO empty" interrupt.
The OTG then sends the host a NAK response. To avoid this
scenario, the application checks the GINSTS.FetSusp interrupt,
which ensures that the FIFO is full before clearing a global NAK
handshake.
Alternatively, the application masks the "IN token received when
FIFO empty" interrupt if clearing a global IN NAK handshake.
Incomplete Periodic Transfer. In Host mode, the core sets this
interrupt bit if there are incomplete periodic transactions still
pending which are scheduled for the current microframe.
Incomplete Isochronous OUT Transfer. The Device mode, the
core sets this interrupt to indicate that there is at least one
isochronous OUT endpoint on which the transfer is not complete
in the current microframe. This interrupt is asserted along with the
End of Periodic Frame Interrupt (EOPF) bit in this register.
Incomplete Isochronous IN Transfer. The core sets this interrupt
to indicate that there is at least one isochronous IN endpoint on
which the transfer is not complete in the current microframe. This
interrupt is asserted along with the End of Periodic Frame
Interrupt (EOPF) bit in this register.
OUT Endpoints Interrupt. The core sets this bit to indicate that an
interrupt is pending on one of the OUT endpoints of the core (in
Device mode). The application must read the Device All Endpoints
Interrupt (DAINT) register to determine the exact number of the
OUT endpoint on which the interrupt occurred, and then read the
corresponding Device OUT Endpoint-n interrupt (DOEPINTn)
register to determine the exact cause of the interrupt. The
application must clear the appropriate status bit in the
corresponding DOEPINTn register to clear this bit.
Description
USB2.0 HS OTG
R/W Reset
Value
R_SS 1'b0
_WC
R_SS 1'b0
_WC
R_SS 1'b0
_WC
R 1'b0
8.10-31