Samsung S5PC100 User Manual page 411

DRAM CONTROLLER
ctrl_shiftc
Use DQS cleaning to remove high-Z state of DQS.
ctrl _ gate
D Q
FF
CK
Controller
Figure 5.1-11 Board Level Connection Diagram for DQS Cleaning.
5.1-28
Phase Delay for DQS Cleaning
GATEout signal delay amount for DDR. If this field is fixed, this
should not be changed during operation. This value is valid
after ctrl_resync becomes HIGH and LOW.
0x000 = T/128 (2.8125' shift),
0x001 = T/64 (5.625' shift),
0x010 = T/32 (11.25' shift),
[2:0] 0x011 = T/16 (22.5' shift),
0x100 = T/8 (45' shift),
0x101 = T/4 (90' shift),
0x110 = T/2 (180' shift),
0x111 = T (360' shift)
Recommended values according to memory type :
0x100 when LPDDR/LPDDR2,
0x110 when DDR2
NOTE : DQS CLEANING SCHEME
PHY
io _ gate _ out
tDL
delay
line
to each
data slice
data _ slice
DQS
delay
line Clean
Q D
FF
CK
IO
io _ ck _ out IO
tA tB
tA
Feed -back
IO
D C
IO
io _ gate _ in
tE
I/O
tE tB
io _ dqs _ in
IO
IO
S5PC100 USER'S MANUAL (REV1.0)
IO
CK
IO
tC tD
GATEO
B A
GATEI
tC tD
IO
IO
R/W 0x0
Memory
ADCT /
CMD
CK /CK
B
tAC
DQS
DQ