Samsung S5PC100 User Manual page 570

DMA CONTROLLER
3.2.9 Configuration Register0 for DMA_mem (CR0, R, Address=0xE810_0E00)
CR0
num_events
num_periph_req
num_chnls
mgr_ns_at_rst
boot_en
periph_req
3.2.10 Configuration Register1 for DMA_MEM (CR1, R, Address=0xE810_0E04)
CR1
num_i-cache_lines
i-cache_len
6.1-22
Bit
Number of interrupt outputs that the DMAC provides
[21:17]
b11111 = 32 interrupt outputs, irq[31:0]
Number of peripheral request interfaces that the DMAC
provides
[16:12]
b00001 = 2 peripheral request interfaces
Number of DMA channels that the DMAC supports
[6:4]
b111 = 8 DMA channels
Indicates the status of the boot_manager_ns signal when the
DMAC exited from reset
[2]
0 = boot_manager_ns was LOW
Indicates the status of the boot_from_pc signal when the
DMAC exited from reset
[1]
0 = boot_from_pc was LOW
Supports peripheral requests
[0]
1 = the DMAC provides the number of peripheral request
interfaces that the num_periph_req field specifies.
Bit
Read value is always 7. It means DMA_MEM has 8 i-cache
[7:4]
lines.
Read value is always 5. It means the length of an i-cache
[2:0]
line is 32 bytes.
S5PC100 USER'S MANUAL (REV1.0)
Description
Description
Reset Value
0x1F
0x1
7
0
0
1
Reset Value
0x7
0x5