Dma Controller - Samsung S5PC100 User Manual

S5PC100 USER'S MANUAL (REV1.0)
6.1
1 OVERVIEW
S5PC100 supports 2 Direct Memory Access (DMA) tops, one for Memory to Memory (M2M) transfer (DMA_mem),
and the other one for Peripheral to memory transfer and vice-versa (DMA_peri). The M2M DMA top consists of a
PL330 and some logics. The Peri DMA top consists of two PL330s, and dma_map.
IRQ to
interrupt controller
DMA_mem
DMA (PL330)
Conv
erter
SEC_ SEC _
SEC_
TX_REQ RX_REQ
TX_CLR
All peripherals must be set as non-secure at TZPC module, because DMA_peri operates only as non-secure.
Bus interface of PL330 is AXI, so that DMA_mem is attached to AXI_B0, and DMA_peri is attached to AXI_B1
(For more information, refer

DMA CONTROLLER

DMA_peri
Conv
erter
Conv
erter
SEC_
RX_CLR
Figure 6.1-1 Two DMA Tops
"03.01.Bus Configuration"
IRQ to
interrupt controller
DMA0 (PL330)
Conv Conv
erter erter
BREQ 0[31:0]
CLR 0[31:0]
dma_map
REQ from IPs
chapter).
DMA CONTROLLER
IRQ to
interrupt controller
DMA 1 (PL330 )
Conv Conv
erter erter
BREQ1[31:0]
(only wires and OR-gates)
ACK to IPs
Conv
erter
CLR 1[31:0]
6.1-1