Samsung S5PC100 User Manual page 906

S5PC100 USER'S MANUAL (REV1.0)
8.2.40 Device IN Token Sequence Learning Queue Read Register 1 (DTKNQR1, R, Address =
0xED20_0820)
The queue is 4 bits wide to store the endpoint number. A read from this register returns the first 5 endpoint entries
of the IN Token Sequence Learning Queue. If the Queue is full, the new token is pushed into the queue and
oldest token is discarded.
DTKNQR1 Bit
EPTkn [31:8]
WrapBit [7]
Reserved [6:5]
INTKnWPtr [4:0]
8.2.41 Device IN Token Sequence Learning Queue Read Register 2 (DTKNQR2, R, Address =
0xED20_0824)
Read from this register returns the next 8 endpoint entries of the learning queue.
DTKNQR2 Bit
EPTkn [31:0]
Endpoint Token
Four bits per token represent the endpoint number of the token :
• Bits [31:28] : Endpoint number of Token 5
• Bits [27:24] : Endpoint number of Token 4
• • •
• Bits [15:12] : Endpoint number of Token 1
• Bits [11:8] : Endpoint number of Token 0
Wrap Bit
This bit is set if the write pointer wraps. It is cleared if the
learning queue is cleared.
-
IN Token QUEUE Write Pointer
Endpoint Token
Four bits per token represent the endpoint number of the token:
• Bits [31:28] : Endpoint number of Token 13
• Bits [27:24] : Endpoint number of Token 12
• • •
• Bits [7:4] : Endpoint number of Token 7
• Bits [3:0] : Endpoint number of Token 6
Description
Description
USB2.0 HS OTG
R/W Reset Value
R 24'h0
R 1'b0
R 2'h0
R 5'h0
R/W Reset
Value
R 32'h0
8.10-63