Samsung S5PC100 User Manual page 985

SD/MMC CONTROLLER
9.16 SOFTWARE RESET REGISTER
Software Reset Register
•
SWRST0, R/W, Address = 0xED80_002F
•
SWRST1, R/W, Address = 0xED90_002F
•
SWRST2, R/W, Address = 0xEDA0_002F
A reset pulse is generated when writing 1 to each bit of this register. After completing the reset, the Host
Controller clears each bit. Because it takes time to complete software reset, the SD Host Driver confirms that
these bits are 0.
SWRST Bit
Reserved [7:3]
RSTDAT [2]
RSTCMD [1]
RSTALL [0]
8.12-50
Reserved
Software Reset For DAT Line
Only part of data circuit is reset. DMA circuit is also reset. (RWAC)
The following registers and bits are cleared by this bit:
Buffer Data Port register
Buffer is cleared and initialized.
Present State register
Buffer Read Enable
Buffer Write Enable
Read Transfer Active
Write Transfer Active
DAT Line Active
Command Inhibit (DAT)
Block Gap Control register
Continue Request
Stop At Block Gap Request
Normal Interrupt Status register
Buffer Read Ready
Buffer Write Ready
DMA Interrupt
Block Gap Event
Transfer Complete
'1' = Reset
'0' = Work
Software Reset For CMD Line
Only part of command circuit is reset. (RWAC).
The following registers and bits are cleared by this bit:
Present State register
Command Inhibit (CMD)
Normal Interrupt Status register
Command Complete
'1' = Reset
'0' = Work
Software Reset For All
This reset affects the entire Host Controller except for the card detection
circuit. Register bits of type ROC, RW, RW1C, RWAC, HWInit are cleared
Description
S5PC100 USER'S MANUAL (REV1.0)
Reset Value
0
0
0
0