Samsung S5PC100 User Manual page 785

S5PC100 USER'S MANUAL (REV1.0)
DSIM_INTMSK
Reserved
MskControl2
MskControl1
MskControl0
MskContentLP0
MskContentLP1
3.2.14 Packet Header FIFO register (DSIM_PKTHDR, W, Address = 0xECB0_0x34)
This register is the FIFO for packet header to send DSI packets.
DSIM_PKTHDR
Reserved
PacketHeader
3.2.15 Payload FIFO register (DSIM_PAYLOAD, W, Address = 0xECB0_0x38)
This register is the FIFO for payload to send DSI packets.
DSIM_PAYLOAD
Payload
Bit
(For more information refer to standard d-phy
specification)
[5] Reserved
[4] Control Error lane2
(For more information refer to standard d-phy
specification)
[3] Control Error lane1
(For more information refer to standard d-phy
specification)
[2] Control Error lane0
(For more information refer to standard d-phy
specification)
[1] LP0 Contention Error
(For more information refer to standard d-phy
specification)
[0] LP1 Contention Error
(For more information refer to standard d-phy
specification)
Bit
[31:24] Reserved
[23:0] This register is to write the packet header of Tx packet.
[7:0] = DI
[15:8] = Dat0 (Word Count lower byte for long packet)
[23:16] = Dat1 (Word Count upper byte for long
packet)
Bit
[31:0] This register is to write the Payload of Tx packet.
Description
Description
Description
MIPI DSIM
R/W Reset Value
- -
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W Reset Value
- -
W 0
R/W Reset Value
W 0
8.7-29