Samsung S5PC100 User Manual page 374

VECTORED INTERRUPT CONTROLLER
4.1 IRQ STATUS REGISTER
(VICIRQSTATUS, R, ADDRESS=0XE400_0000, 0XE410_0000, 0XE420_0000)
VICIRQSTATUS Bit
IRQStatus [31:0]
4.2 FIQ STATUS REGISTER
(VICFIQSTATUS, R, ADDRESS=0XE400_0004, 0XE410_0004, 0XE420_0004)
VICFIQSTATUS Bit
FIQStatus [31:0]
4.3 RAW INTERRUPT STATUS REGISTER
(VICRAWINTR, R, ADDRESS=0XE400_0008, 0XE410_0008, 0XE420_0008)
VICRAWINTR Bit
RawInterrupt [31:0]
4.1-18
Shows the status of the interrupts after masking by the
VICINTENABLE and VICINTSELECT Registers:
0 = Interrupt is inactive
1 = Interrupt is active.
There is one bit of the register for each interrupt source.
Shows the status of the FIQ interrupts after masking by the
VICINTENABLE and VICINTSELECT Registers:
0 = Interrupt is inactive
1 = Interrupt is active.
There is one bit of the register for each interrupt source.
Shows the status of the FIQ interrupts before masking by the
VICINTENABLE and VICINTSELECT Registers:
0 = Interrupt is inactive before masking
1 = Interrupt is active before masking
Because this register provides a direct view of the raw interrupt
inputs, the reset value is unknown.
There is one bit of the register for each interrupt source.
S5PC100 USER'S MANUAL (REV1.0)
Description
Description
Description
Reset Value
0x00000000
Reset Value
0x00000000
Reset Value
-