Samsung S5PC100 User Manual page 869

USB2.0 HS OTG
8.2.7 OTG AHB Configuration Register (GAHBCFG, R/W, Address = 0xED20_0008)
This register configures the core after power-on or a change in mode of operation. This register mainly contains
AHB system-related configuration parameters. Do not change this register after the initial programming. The
application must program this register before starting any transactions on either the AHB or the USB.
GAHBCFG Bit
Reserved [31:9]
PTxFEmpLvl [8]
NPTxFEmp [7]
Lvl
Reserved [6]
DMAEn [5]
HBstLen [4:1]
GlblIntrMsk [0]
8.10 -26
-
Periodic TxFIFO Empty Level
Indicates if the Periodic TxFIFO Empty Interrupt bit in the Core
Interrupt registers (GINTSTS.PTxFEmp) is triggered. This bit is
used only in Slave mode.
• 1'b0 : GINTSTS.PTxFEmp interrupt indicates that the Periodic
TxFIFO is half empty
• 1'b1 : GINTSTS.PTxFEmp interrupt indicates that the Periodic
TxFIFO is completely empty
Non-Periodic TxFIFO Empty Level
Indicates if the Non-Periodic TxFIFO Empty Interrupt bits in the
Core Interrupt register (GINSTS.NPTxFEmp) is triggered. This bit
is used only in Slave mode.
• 1'b0 : GINTSTS.NPTxFEmp interrupt indicates that the Non-
Periodic TxFIFO is half empty
• 1'b1 : GINTSTS.NPTxFEmp interrupt indicates that the Non
Periodic TxFIFO is completely empty
-
DMA Enable
• 1'b0 : Core operates in Slave mode
• 1'b1 : Core operates in a DMA mode
Burst Length/vType
Internal DMA Mode − AHB Master burst type:
• 4'b0000 : Single
• 4'b0001 : INCR
• 4'b0011 : INCR4
• 4'b0101 : INCR8
• 4'b0111 : INCR16
• Others : Reserved
Global Interrupt Mask
The application uses this bit to mask or unmask the interrupt line
assertion to itself.
• 1'b0 : Mask the interrupt assertion to the application
• 1'b1 : Unmask the interrupt assertion to the application
Description
S5PC100 USER'S MANUAL (REV1.0)
R/W
R/W
R/W
R/W
R/W
R/W
Reset
Value
23'h0
1'b0
1'b0
1'b0
1'b0
4'b0
1'b0