Samsung S5PC100 User Manual page 880

S5PC100 USER'S MANUAL (REV1.0)
8.2.12 Receive Status Debug Read/Status Read and Pop Registers (GRXSTSR/GRXSTSP)
A read to the Receive Status Debug Read register returns the contents of the top of the Receive FIFO. A read to
the Receive Status Read and Pop register additionally pops the top data entry out of the RxFIFO.
The receive status contents must be interpreted differently in Host and Device modes. The core ignores the
receive status pop/ read if the receive FIFO is empty and returns a value of 32'h0000_0000. The application must
only pop the Receive Status FIFO if the Receive FIFO Non-Empty bit of the Core Interrupt register
(GINTSTS.RxFLvl) is asserted.
8.2.13 Host Mode Receive Status Debug Read/Status Read and Pop Registers (GRXSTSR/GRXSTSP, R,
Address = 0xED20_001C, 0xED20_0020)
GRXSTSR/
GRXSTSP
Reserved [31:21] -
PktSts [20:17] Packet Status
DPID [16:15] Data PID
BCnt [14:4]
ChNum [3:0]
Bit
Indicates the status of the received packet.
• 4'b0010 : IN data packet received
• 4'b0011 : IN transfer completed (triggers an interrupt)
• 4'b0101 : Data toggle error (triggers an interrupt)
• 4'b0111 : Channel halted (triggers an interrupt)
• others : Reserved
Indicates the Data PID of the received packet.
• 2'b00 : DATA0
• 2'b10 : DATA1
• 2'b01 : DATA2
• 2'b11 : MDATA
Byte Count
Indicates the byte count of the received IN data packet.
Channel number
Indicates the channel number to which the current received
packet belongs.
Description
USB2.0 HS OTG
R/W Reset Value
-
R -
R -
R -
R -
8.10-37