Samsung S5PC100 User Manual page 482

S5PC100 USER'S MANUAL (REV1.0)
NFCONT
MLCStop
EnbIllegalAccINT
EnbRnBINT
RnB_TransMode
MECCLock
SECCLock
InitMECC
InitSECC
HW_nCE
Reg_nCE1
Reg_nCE0
MODE
Bit
1 = Enables interrupt
[11] 8-bit ECC encoding/ decoding operation initialization
Illegal access interrupt control
0 = Disables interrupt
1 = Enables interrupt
[10]
Illegal access interrupt occurs if CPU tries to program or erase
locking area (the area setting in NFSBLK (0xE720_0020) to
NFEBLK (0xE720_0024)-1.
RnB status input signal transition interrupt control
[9]
0 = Disables RnB interrupt
1 = Enables RnB interrupt
RnB transition detection configuration
[8]
0 = Detects rising edge
1 = Detects falling edge
Lock Main area ECC generation
0 = Unlocks Main area ECC
[7] 1 = Locks Main area ECC
Main area ECC status register is
NFMECC0/NFMECC1(0xE720_0034/0xE720_0038),
Lock Spare area ECC generation.
0 = Unlocks Spare ECC
[6]
1 = Locks Spare ECC
Spare area ECC status register is NFSECC(0xE720_003C),
[5] 1 = Initialize main area ECC decoder/ encoder (write-only)
[4] 1 = Initialize spare area ECC decoder/ encoder (write-only)
[3] Reserved (HW_nCE)
[2] NAND Flash Memory nRCS[1] signal control
NAND Flash Memory nRCS[0] signal control
[1]
0 = Force nRCS[0] to low (Enables chip select)
1 = Force nRCS[0] to High (Disables chip select)
NAND Flash controller operating mode
[0]
0 = Disables NAND Flash Controller
1 = Enables NAND Flash Controller
Description
NAND FLASH CONTROLLER
Reset Value
0
0
0
0
1
1
0
0
0
1
1
0
5.4-17