Samsung S5PC100 User Manual page 414

S5PC100 USER'S MANUAL (REV1.0)
4.2.9 PHY Control2 Register (PhyControl2, R/W, Address=0xE600_0020)
PHYCONTROL2
Reserved
ctrl_offset3 [30:24]
Reserved
ctrl_offset2 [22:16]
Reserved
ctrl_offset1 [14:8]
Reserved
ctrl_offset0
Bit
[31] Should be zero
This field is for debug purpose.
If this field is fixed, this should not be changed during
operation. This value is valid after ctrl_resync becomes HIGH
and LOW.
rd_slice_3 offset amount :
ctrl_offset3[6] = 1 : (tFS : fine step delay)
90' delay amount - ctrl_offset0[5:0] x tFS
ctrl_offset3[6] = 0 :
90' delay amount + ctrl_offset0[5:0] x tFS
[23] Should be zero
This field is for debug purpose.
If this field is fixed, this should not be changed during
operation. This value is valid after ctrl_resync becomes HIGH
and LOW.
rd_slice_2 offset amount :
ctrl_offset2[6] = 1 : (tFS : fine step delay)
90' delay amount - ctrl_offset0[5:0] x tFS
ctrl_offset2[6] = 0 :
90' delay amount + ctrl_offset0[5:0] x tFS
[15] Should be zero
This field is for debug purpose.
If this field is fixed, this should not be changed during
operation. This value is valid after ctrl_resync becomes HIGH
and LOW.
rd_slice_1 offset amount :
ctrl_offset1[6] = 1 : (tFS : fine step delay)
90' delay amount - ctrl_offset0[5:0] x tFS
ctrl_offset1[6] = 0 :
90' delay amount + ctrl_offset0[5:0] x tFS
[7] Should be zero
This field is for debug purpose.
If this field is fixed, this should not be changed during
operation. This value is valid after ctrl_resync becomes HIGH
and LOW.
rd_slice_0 offset amount :
[6:0]
ctrl_offset0[6] = 1 : (tFS : fine step delay)
90' delay amount - ctrl_offset0[5:0] x tFS
ctrl_offset0[6] = 0 :
90' delay amount + ctrl_offset0[5:0] x tFS
Description
DRAM CONTROLLER
Reset
R/W
Value
0x0
R/W 0x0
0x0
R/W 0x0
0x0
R/W 0x0
0x0
R/W 0x0
5.1-31