Samsung S5PC100 User Manual page 629

S5PC100 USER'S MANUAL (REV1.0)
If the transmitter transfers data from its transmit FIFO register to its transmit shifter and the number of data left in
transmit FIFO reaches Tx FIFO Trigger Level, Tx interrupt is generated (provided Transmit mode in control
register is selected as Interrupt request or polling mode). In Non-FIFO mode, transferring data from the transmit
holding register to transmit shifter causes Tx interrupt under the Interrupt request and polling mode.
Remember that the Tx interrupt is always requested if the number of data in the transmit FIFO is smaller than the
trigger level. This means that an interrupt is requested as soon as you enable the Tx interrupt unless you fill the Tx
buffer prior to that. It is recommended to fill the Tx buffer first and then enable the Tx interrupt.
The interrupt controllers of S5PC100 are level-triggered type. You must set the interrupt type as 'Level' if you
program the UART control registers.
If Receive mode and Transmit mode in control register are selected as DMAn request mode then DMAn request
occurs instead of Rx or Tx interrupt in the above situation.
Type
Rx interrupt Generated if received data reaches the trigger
level of received FIFO.
Generated if the number of data in FIFO does not
reaches Rx FIFO trigger Level and does not
receive any data during 3 word time (receive time
out). This interval follows the setting of Word
Length bit.
Tx interrupt Generated if transmit data reaches the trigger
level of transmit FIFO (Tx FIFO trigger Level).
Error Generated if frame error, parity error, or break
interrupt signal are detected.
Generated if it gets to the top of the receive FIFO
without reading out data in it (overrun error).
3.7 UART ERROR STATUS FIFO
UART has the error status FIFO besides the Rx FIFO register. The error status FIFO indicates which data, among
FIFO registers, is received with an error. An error interrupt is issued only if the data, which has an error, is ready
to read out. To clear the error status FIFO, the URXHn with an error and UERSTATn must be read out.
For example, it is assumed that the UART Rx FIFO receives A, B, C, D, and E characters sequentially and the
frame error occurs while receiving 'B', and the parity error occurs while receiving 'D'.
The actual UART receive error does not generate any error interrupt, since the character, which was received with
an error, has not been read yet. The error interrupt occurs if the character is read out.
Table 8.1-1 Interrupts in Connection with FIFO
FIFO Mode Non-FIFO Mode
Generated by receive holding register
whenever receive buffer becomes full.
Generated by transmit holding register
whenever transmit buffer becomes
empty.
Generated by all errors. However if
another error occurs at the same time,
only one interrupt is generated.
UART
8.1-5