Samsung S5PC100 User Manual page 213

Power Management S5PC100 USER'S MANUAL (REV1.0)
Then PMU performs the following sequence to exit DEEP-STOP mode (TOP_LOGIC_ON = 1'b1).
1. Enables the OSC pads if disabled and wait for the OSC stabilization (around 1ms).
2. Enables the PLLs and wait for locking (300us).
3. Unmasks clock input to clock-on blocks.
4. Initiates DRAMs to exit self-refresh mode.
PMU performs the following sequence to exit DEEP-STOP mode (TOP_LOGIC_ON = 1'b0).
1. Enables the OSC pads if disabled and wait for the OSC stabilization (around 1ms).
2. Unmasks clock input to clock-on blocks
3. S/W sets system initialization including GPIO register setting since normal F/F lost information due to power-
gating.
4. S/W sets IO_RET_RELEASE bit of OTHERS register to 1'b1 to release retention for I/O pad.
5. S/W sets PLL initial setting (P/M/S value).
6. S/W sets to Enable the PLLs and wait for locking (about 300us).
7. S/W sets initialization configurations in LPCON (DRAM controller) to access to/from DRAM.
3.7 SLEEP MODE
In SLEEP mode, all power domains are powered down except for ALIVE and RTC, all PLLs are disabled, and the
oscillators (OSCs) except that for the RTC are selectively disabled. Since the external regulator becomes off using
control signal from S5PC100, you should consider waiting time for the regulator stabilization in the SLEEP mode
wake-up using PWR_STABLE register.
To enter SLEEP mode:
1. Set NORMAL_CFG[5] to 1'b0 so that Audio domain becomes power-off to prevent current leakage from
occurring in I2S0 related I/O pad (Xi2s0CDCLK, Xi2s0LRCK, Xi2s0SCLK, Xi2s0SDI, Xi2s0SDO[2:0]).
2. Check that BLK_PWR_STAT[5] becomes 1'b0 to confirm Audio domain is power-off.
3. Set CFG_STANDBYWFI field of PWR_CFG to 2'b11.
4. Set PMU_INT_DISABLE bit of OTHERS register to 1'b1 to prevent interrupts from occurring while entering
SLEEP mode.
5. Execute Wait For Interrupt instruction (WFI).
Then PMU performs the following sequence to enter SLEEP mode.
1. Completes all active bus transactions.
2. Completes all active memory controller transactions.
3. Initiates the external DRAM enter self-refresh mode (to preserve DRAM contents).
4. Power down all power domains except the already power-down domains
5. Disables all PLLs.
6. Selectively disables OSCs except 32.768kHz.
7. XPWRRGTON becomes low to power off external voltage regulator.
To exit SLEEP mode:
• Various types of wakeup sources are used. Wakeup sources referred in Section 5 WAKEUP SOURCES.
Then PMU performs the following sequence to exit SLEEP mode.
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