Samsung S5PC100 User Manual page 233

Power Management S5PC100 USER'S MANUAL (REV1.0)
7.3 SOFTWARE RESET
Software reset is asserted when S/W writes "0xC100" to SWRESET register (@0xE020_0000) in NORMAL mode.
During the software reset, the following actions occur:
• All units (except some registers listed in Table 2.4-15) go into their pre-defined reset state.
• All pins get their reset state, and XnBATF pin is ignored.
• The XnRSTOUT pin is asserted during software reset.
If Software reset is asserted the following sequence occurs.
1. PMU requests AXI masters and AHB-to-AXI bridges to finish current transactions.
2. Bus controller send acknowledge to PMU after completed bus transactions.
3. PMU request memory controller to enter self refresh mode.
4. PMU waits for self refresh acknowledge from memory controller.
5. Internal reset signals and XnRSTOUT are asserted and reset counter is activated.
6. Reset counter is expired then; internal reset signals and XnRSTOUT are released.
Timing diagram for software reset is shown in Figure 2.4-7.
Figure 2.4-7 Software Reset Timing Diagram
2.4-34