Samsung S5PC100 User Manual page 872

S5PC100 USER'S MANUAL (REV1.0)
GRSTCTL Bit
HSftRst [1]
CSftRst [0]
HClk Soft Reset
The application uses this bit to flush the control logic in the AHB
Clock domain. Only AHB Clock Domain pipelines are reset.
• FIFOs are not flushed with this bit.
• All state machines in the AHB clock Domain are reset to IDLE
state after terminating the transactions on the AHB, following the
protocol.
• Control bits in the CSRs that the AHB Clock domain state
machines use are cleared.
• Status mask bits generated by the AHB Clock domain state
machine that control the interrupt status, are cleared to clear the
interrupt.
• Because interrupt status bits are not cleared, the application
gets the status of any core events that occurred after this bit is
set.
This is a self-clearing bit that the core clears after all necessary
logic is reset in the core. This may take several clocks,
depending on the core's current state.
Core Soft Reset
Resets the hclk and phy_clock domains as follows:
• Clears the interrupts and all the CSR registers except the
following register bits:
- HCFG.FSLSPclkSel
- DCFG.DevSpd
• All module state machines (except the AHB Slave Unit) are
reset to the IDLE state, and all the transmit FIFOs and the
receive FIFO are flushed.
• Any transactions on the AHB Master are terminated as soon as
possible, after gracefully completing the last data phase of an
AHB transfer. Any transactions on the USB are terminated
immediately.
The application can write to this bit any time it wants to reset the
core. This is a self-clearing bit and the core clears this bit after all
the necessary logic is reset in the core, which may take several
clocks, depending on the current state of the core. Once this bit
is cleared software must wait at least 3 PHY clocks before doing
any access to the PHY domain. Software must also check that
bit 31 of this register is 1 (AHB Master is IDLE) before starting
any operation. Typically software reset is used during software
development and if you dynamically change the PHY selection
bits in the USB configuration registers listed above. If you
change the PHY, the corresponding clock for the PHY is
selected and used in the PHY domain. Once a new clock is
selected, the PHY domain has to be reset for proper operation.
Description
USB2.0 HS OTG
R/W Reset
Value
R_WS 1'b0
_SC
R_WS 1'b0
_SC
8.10-29