Samsung S5PC100 User Manual page 572

DMA CONTROLLER
3.2.14 Configuration Register DN for DMA_MEM (CRdn, R, Address=0xE810_0E14)
CRDn
data_buffer_dep
rd_q_dep
rd_cap
wr_q_dep
wr_cap
data_width
6.1-24
Bit
The number of lines that the data buffer contains
[29:20]
b000011111 = 32 lines
The depth of the read queue
[19:16]
b0111 = 8 lines
Read issuing capability that programs the number of
outstanding read transactions
[14:12]
b011 = 4
The depth of the write queue
[11:8]
b0111 =8 lines
Write issuing capability that programs the number of
outstanding write transactions
[6:4]
b011 = 4
The data bus width of the AXI interface
[2:0]
b011 = 64-bit
S5PC100 USER'S MANUAL (REV1.0)
Description Reset Value
0x1F
0x7
0x3
0x7
0x3
0x3